1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to flash memory devices with a high coupling ratio and a method of manufacture thereof.
2. Description of Related Art
In the current state of the art, contactless drain (buried diffusion) results in low read currents which is not suitable for high speed random access devices.
U.S. Pat. No. 5,556,799 of Hong for a xe2x80x9cProcess for Fabricating A Flash EEPROMxe2x80x9d Hong teaches that as flash EEPROM devices are made with finer resolutions, floating gate surface areas shrink. This decreases the capacitance of the effective capacitor between the floating gate layer and the control gate layer. The unwanted decrease in effective capacitance results in a reduction in the coupling ratio, which is a parameter that describes the coupling to the floating gate of the voltage present at the control gate of the device. The poor coupling of voltage to a floating gate limits the programming and accessing speed of the flash EEPROM device.
U.S. Pat. No. 5,554,544 of Hsu shows a non-uniform gate oxide created by the field oxide. However, the method/structure differs from the present invention.
Yosiaki S. Hisamune, et al., xe2x80x9cA High Capacitivexe2x80x94Coupling Ratio (HiCR) Cell For 3V Only 64 Mbit And Future Flash Memoriesxe2x80x9d, (1993) IEDM pp. 93-19 to 93-22 describes at page 93-19 xe2x80x9cgate dielectrics consist of 20-nm thick thermal oxide grown on the channel region and 7.5-nm thick silicon oxynitride formed underneath the floating-gate sidewalls. The cell is designed to have ultra small tunneling regions (0.2 xcexcmxc3x970.4 xcexcm) and a large floating gate area (1.4 xcexcmxc3x970.4 xcexcm) in order to obtain the high capacitive-coupling ratio of 0.8. Here the capacitive coupling ratio CRE is defined by       C    RE    =            C      FG              C      T      
xe2x80x9cwhere CFG is the capacitance of the interpoly oxide-nitride-oxide (ONO) dielectrics between the control gate and the floating gate and CT is the total capacitance of the floating gate.xe2x80x9d
An object of this invention is to achieve a high coupling ratio.
Another object of this invention is to provide a non-uniform gate oxide to a achieve a high coupling ratio.
A CMOS compatible process is provided which requires only one additional mask. There is a high coupling ratio due to the non-uniform gate oxide. In addition, a Large Angle Tilted Implant (LATI) process is employed to extend the N+ region to a thicker gate oxide.
In accordance with this invention, a semiconductor memory device with floating gate electrode, an interelectrode dielectric layer and a control gate electrode includes a doped silicon semiconductor substrate covered with variable thickness silicon oxide regions on the surface thereof, the silicon oxide regions being substantially thicker beneath the center of the floating gate electrode, and source/drain regions in the substrate extending beneath the tunnel oxide regions.
Preferably, the variable thickness silicon oxide regions comprise tunnel oxide regions on either side of a gate oxide region, the floating gate electrode being composed of doped polysilicon and including reoxidized polysilicon dielectric regions formed in the floating gate electrode above the junctions of the tunnel oxide regions and the gate oxide region; the silicon oxide comprises a tunnel oxide layer with a thickness from about 80 xc3x85 to about 100 xc3x85 and a gate oxide layer with a thickness from about 150 xc3x85 to about 200 xc3x85; and/or the floating gate is formed with sections reaching down on either side of the reoxidized dielectric regions to the gate oxide region layer and to the tunnel oxide region layers.
Further in accordance with this invention, a semiconductor memory device includes the following. A doped silicon semiconductor substrate has alternating silicon oxide regions formed on the surface thereof. The alternating silicon oxide regions comprising alternating tunnel oxide layer regions and gate oxide layer regions formed on the surface of the substrate with the gate oxide region layers being substantially thicker than the tunnel oxide layer regions. A floating gate electrode is centered over a the gate oxide region and over the tunnel oxide regions on either side of the gate oxide region. Source/drain regions in the substrate extending beneath the tunnel oxide regions.
Preferably, the floating gate electrode is composed of doped polysilicon and includes reoxidized polysilicon dielectric regions formed in the floating gate electrode above the junctions of the tunnel oxide regions and the gate oxide region; the silicon oxide comprises a tunnel oxide layer with a thickness from about 80 xc3x85 to about 100 xc3x85 and a gate oxide layer with a thickness from about 150 xc3x85 to about 200 xc3x85, and/or the floating gate is formed with sections reaching down on either side of the reoxidized dielectric regions to the gate oxide region layer and to the tunnel oxide region layers.